Both CPUs have a maximum of 16MB 元 cache, which can be accessed by 1 thread at most without having to perform expensive remote accesses to the 元 cache of the other CCX module. The reason why the Ryzen 5000 APU should compete against a Zen 2 CPU is obvious. The Zen 2 processor is configured in the BIOS so that only one CCD with 8 cores remains active. This is most likely due to AIDA64's test depth does not go far enough. This gives us comparable conditions as the clock speed affects RAM latency. To better assess the optimization status of Cezanne's design a fixed clock speed of 4GHz is chosen, which is applied to both the 5700G and the 3950X. In absolute terms, we publish the figures with reservations. Relative statements should be possible based on the AIDA64 results for now. We will therefore use other tools in the future. Comparisons with other tools indeed suggest that the criticism is justified. In essence, the criticism is that the values are too low, which could be due to the fact that the test depth is set too low. The tool has recently faced a certain amount of criticism from well-known reviewers regarding the consistency and the implemented methodology. We will now take a look at the memory latencies with the AIDA64 memory benchmark. The transition from the ring bus to the IF costs additional cycles, so it is basically to be expected that the memory latencies do not turn out as good as with an Intel CPU.ĭie Shot by Fritzchens Fritz, Annotation by Locuza Since the Hot Chips 2021 it is known that Zen 3 has a ring bus to connect the cache slices. Can the monolithic design help to at least partially compensate for this?Ī look at a die shot from Cezanne tells us that the memory controller is connected to the cache slices via the Infinity Fabric. Knowledgeable users know that this has a negative impact on access latencies. The dies are interconnected via the Infinity Fabric to exchange data. The memory controller is located on a separate I/O die. In contrast, the Chilplet design of Matisse and Vermeer implement a clear separation of the functional units. This applies in particular to the memory controller. As a bonus, we also compare the performance of the boxed cooler to a high-end air cooler from Noctua.Ĭezanne is designed in such a way that all units of the CPU are located on a single die. IPC comparisons and overclocking results are at the forefront. We will take a closer look at how this affects gaming performance. Basically, it should be noted that the new APUs undoubtedly bring some compelling strengths, such as very good efficiency and high application IPC thanks to the Zen 3 cores but the design leads to high memory latencies despite a monolithic approach.
The launch reviews have already been published a few weeks ago, but we want to look at Cezanne from a different perspective. Previously, the distribution of the CPUs was only limited to the OEM market.
AMD's Ryzen 5000 APUs with Zen 3 architecture are now officially available at retail as of August 5.
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